1. Field of the Invention
The present invention relates to power converters, and, more specifically, the present invention relates to the control circuit of an interleaved PFC power converter.
2. Description of Related Art
Nowadays power converters outputting more than 75 W take advantage of Power Factor Correction (PFC) to improve power factor of AC power and to improve efficacy. To improve efficacy, a new PFC correction circuit has been proposed, wherein the Interleaved PFC power converter with master/slave switching control circuits is the emphasis of current development.
Referring to FIG. 1, it shows a schematic circuit of the conventional Interleaved PFC power converter with master/slave switching control circuits. As shown in FIG. 1, the control circuit at least includes a master switching control circuit (M) 1 and a slave switching control circuit (S) 2. When a first switch Q1 coupled to the magnetic component L1 is controlled by the master switching control circuit 1 and turned off, a current through the magnetic component L1 is rectified by the rectifier D11 and then stored in a capacitor C1. Meanwhile, When a second switch Q2 coupled to the magnetic component L2 is controlled by the slave switching control circuit 2 and turned off, a current through the magnetic component L2 is rectified by the rectifier D22 and then is stored in the capacitor C1. The energy (the current) stored in the capacitor C1 is utilized as an output voltage VO.
The operation of the Interleaved PFC power converter with master/slave switching control circuits is described as follow: the magnetic component L1 receives a voltage that is obtained by rectifying the input voltage VAC. The master switching control circuit 1 respectively generates a control signal VM and a first switching signal SW1 at a VM1 terminal and an output terminal OPFC1 in response to the signals received by VRMS terminal, IAC terminal, feedback terminal FB, current sensing terminal CS1 and VEA terminal (e.g. feedback signal VFB, current sensing signal VCS1 and error signal VEA . . . etc). The signal received by the VRMS terminal is the voltage that is established on the capacitor C2. The voltage is established on the capacitor C2 after the input voltage VAC is rectified and the rectified input voltage VAC is divided by a voltage divider (that consists of resistance components R15 and R16). The signal received by the IAC terminal is a voltage that is obtained by decaying the rectified input voltage VAC through the resistance component R14. A RC compensation circuit (that consists of the resistance components R17 and capacitor C3) is connected between the VEA terminal and a ground terminal to generate the error signal VEA.
The signal received by the VRMS terminal correlates to the input voltage VAC; the signal received by the IAC terminal correlates to an input current. When the load coupled to the PFC power converter decreases, the feedback signal VFB increases and the error signal VEA decreases. Therefore, the error signal VEA correlates to the load condition (how heavy the load is). The control signal VM is utilized to control the input current to follow the input voltage VAC to reach a high power factor. The first switching signal SW1 controls a first switch Q1.
When the first switch Q1 is controlled by the first switching signal SW1 and turned on, the current sensing signal VCS1 is generated at a resistance component R11 in response to the current through the magnetic component L1. The resistance component R11 is coupled to the first switch Q1 the first switch Q1 is controlled by the master switching control circuit 1 and turned off, the current through the magnetic component L1 is rectified by the rectifier D11 and then is stored in the capacitor C1. Moreover, the feedback signal VFB is generated by dividing the output voltage VO through a voltage divider that consists of the resistance components R12 and R13. The feedback signal VFB is coupled to the feedback terminal FB.
The magnetic component L2 receives the voltage that is obtained by rectifying the input voltage VAC. The slave switching control circuit 2 generates a second switching signal SW2 at an output terminal OPFC2 of the slave switching control circuit 2 in response to the control signal VM and a current sensing signal VCS2 received by a VM2 terminal and a current sensing terminal CS2 of the slave switching control circuit 2. The second switching signal SW2 controls the second switch Q2 coupled to the magnetic component L2. When the second switch Q2 is controlled by the second switching signal SW2 and turned on, the current sensing signal VCS2 is generated at a resistance component R21 in response to the current through the magnetic component L2. The resistance component R21 is coupled to the second switch Q2. When the second switch Q2 is controlled by the second switching signal SW2 and turned off, the current through the magnetic component L2 is rectified by the rectifier D22 and then is stored in the capacitor C1.
Referring to FIG. 2, it shows a schematic circuit of the master/slave switching control circuits of the conventional interleaved PFC power converter with master/slave switching control circuits. Also referring to FIG. 1, the positive/negative input terminals of a voltage error amplifier 11 of the master switching control circuit 1 respectively receive a reference signal VR and the feedback signal VFB. The output terminal of the voltage error amplifier 11 is coupled to the VEA terminal of the master switching control circuit 1 to generate the error signal VEA. A multiplier 12 is coupled to the VEA terminal, the VRMS terminal and the IAC terminal of the master switching control circuit 1 to generate the control signal VM. It is a conventional technology that the multiplier 12 generates the control signal VM, so here it can be omitted.
A current error amplifier 13, a comparator 15 and a sample-hold circuit S-H form a current feedback compensation circuit. The control signal VM is coupled to the negative input terminal of the current error amplifier 13 and to the VM1 terminal of the master switching control circuit 1. The positive input terminal of the current error amplifier 13 receives a signal VS1. The signal VS1 is generated by the sample-hold circuit S-H sampling the current sensing signal VCS1. The current error amplifier 13 generates a signal IEA1 in response to the signal VS1 and the control signal VM. The signal IEA1 is coupled to the positive input terminal of the comparator 15. The negative input terminal of the comparator 15 receives a first saw signal ISAW1 generated by an oscillator 14. The output terminal of the comparator 15 is coupled to the rest terminal R of a flip-flop 16.
The set terminal S and the clock terminal CK of the flip-flop 16 respectively receive an input power VCC and a clock signal CLK generated by the oscillator 14. The output terminal Q of the flip-flop 16 is coupled to the output terminal OPFC1 of the master switching control circuit 1 and outputs the first switching signal SW1. The reset terminal R of the flip-flop 16 is controlled by the output terminal of the comparator 15 through a NOT gate. The output terminal of the comparator 15 controls the disabling of the first switching signal SW1 in response to the first saw signal ISAW1 and the signal IEA1. Therefore, when the control signal VM is changed with the adjustment of the load, the output of the comparator 15 will react immediately to control the pulse width of the first switching signal SW1.
Continuously referring to FIG. 2, a current error amplifier 23, a comparator 25 and a sample-hold circuit S-H form a current feedback compensation circuit of the slave switching control circuit 2. The VM2 terminal of the slave switching control circuit 2 is coupled to the VM1 terminal of the master switching control circuit 1 to receive the control signal VM. Therefore, when the control signal VM is generated, the positive input terminal of the current error amplifier 23 will receive the control signal VM through the VM2 terminal of the slave switching control circuit 2. The negative input terminal of the current error amplifier 23 receives a signal VS2. The signal V2 is generated by the sample-hold circuit S-H of the slave switching control circuit 2 sampling the current sensing signal VCS2. The negative input terminal of the current error amplifier 23 is coupled to the CS2 terminal of the slave switching control circuit 2 through the sample-hold circuit S-H to receive the current sensing signal VCS2. The output terminal of the current error amplifier 23 generates the signal IEA2 in response to the control signal VM and the signal VS2.
The positive input terminal and the negative input terminal of the comparator 25 respectively receive a second saw signal ISAW2 and the signal IEA2. The set terminal S and the clock terminal CK of the flip-flop 26 respectively receive the input power VCC and the clock signal CLK. The output terminal Q of the flip-flop 26 is coupled to the output terminal OPFC2 of the slave switching control circuit 2 and outputs the second switching signal SW2. The reset terminal R of the flip-flop 26 is controlled by the output terminal of the comparator 25 through a NOT gate. The output terminal of the comparator 25 controls the disabling of the second switching signal SW2 in response to the second saw signal ISAW2 and the signal IEA2. Wherein, when the control signal VM is changed, the output of the comparator 25 will react immediately to adjust the pulse width of the second switching signal SW2 simultaneously.
The feature of the conventional interleaved PFC power converter with master/slave switching control circuits is that the master switching control circuit 1 and the slave switching control circuit 2 individually control a half output power of the power converter. Therefore, the switching frequency of the first switch Q1 and the second switch Q2 are the same. However, a new standard of efficacy asks that the power converter provides higher system efficacy. Therefore, when the load is light, the new standard of efficacy can be reached by reducing the switching loss of the switch to upgrade the efficacy and it is also the emphasis of the current development of the interleaved PFC power converter with master/slave switching control circuits.